Reference is now made to FIG. 1 which illustrates a block diagram of a prior art event controlled decoding circuit 10. The circuit 10 is configured to receive a plurality of control inputs (C1-Ci) 12 and generate a plurality of output signals (S1-Sj) 14. The output signals 14 are generated by an output register circuit 16. The circuit 10 further includes a logic circuit 18 functioning as a decoder. A counter circuit 20 generates a count signal 22 which is applied to the logic circuit as a reference. The logic circuit 18 receives the control inputs 12, decodes the data of the control inputs and provides signals 24 in response to the count signal 22 to load the output register circuit 16 with data for generating the output signals 14.
The use of logic circuit 18 poses a number of concerns including: difficulty in adapting to required changes in output signal generation, complexity in the logic design in the number of inputs/outputs increases, and sub-optimal logic design. There is a need in the art to address the foregoing problems.